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cy7c1021cv26 1-mbit (64 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05589 rev. *g revised september 30, 2013 1-mbit (64 k 16) static ram features temperature range ? automotive: ?40 c to 125 c high speed ? t aa = 15 ns optimized voltage range: 2.5 v to 2.7 v low active power: 220 mw (max) automatic power-down when deselected independent control of upper and lower bits cmos for optimum speed/power available in pb-free and non pb-free 44-pin tsop ii, 44-pin (400-mil) molded soj and pb-free 48-ball fbga packages functional description the cy7c1021cv26 is a high-performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the end of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). logic block diagram 64 k 16 ram array i/o 0 ?i/o 7 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 2 a 1 i/o 8 ?i/o 15 ce we ble bhe a 8
cy7c1021cv26 document number: 38-05589 rev. *g page 2 of 17 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 pin definitions .................................................................. 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 6 thermal resistance .......................................................... 6 ac test loads and waveforms ....................................... 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ......................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc? solutions ...................................................... 17 cypress developer community ................................. 17 technical support ................. .................................... 17
cy7c1021cv26 document number: 38-05589 rev. *g page 3 of 17 selection guide description [1] -15 unit maximum access time 15 ns maximum operating current 80 ma maximum cmos standby current 10 ma pin configurations figure 1. 44-pin soj/tsop ii pinout [2] figure 2. 48-ball fbga pinout [2] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 13 a 14 a 8 a 9 a 10 a 11 nc a 12 nc oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss nc 10 a 15 we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe nc nc a 2 a 1 ble i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h nc nc v cc v cc v ss notes 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. 2. nc pins are not connected on the die.
cy7c1021cv26 document number: 38-05589 rev. *g page 4 of 17 pin definitions pin name pin number i/o type description a 0 ?a 15 1?5, 18?21, 24?27, 42?44 input address inputs used to select one of the address locations. i/o 0 ?i/o 15 7?10, 13?16, 29?32, 35?38 input/output bidirectional data i/o lines . used as input or output lines depending on operation. nc 22, 23, 28 no connect no connects . this pin is not connected to the die. we 17 input/control write enable input, active low . when selected low, a write is conducted. when selected high, a read is conducted. ce 6 input/control chip enable input, active low . when low, selects the chip. when high, deselects the chip. bhe , ble 40, 39 input/control byte write select inputs, active low . bhe controls i/o 15 ?i/o 8 , ble controls i/o 7 ?i/o 0 . oe 41 input/control output enable, active low . controls the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when de-asserted high, i/o pins are tri-stated, and act as input data pins. v ss 12, 34 ground ground for the device . should be connected to ground of the system. v cc 11, 33 power supply power supply inputs to the device.
cy7c1021cv26 document number: 38-05589 rev. *g page 5 of 17 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [3] .................................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [3] .................................. ?0.5 v to v cc + 0.5 v dc input voltage [3] .............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v cc automotive ?40 ? c to +125 ? c 2.5 v?2.7 v electrical characteristics over the operating range parameter description test conditions -15 unit min max v oh output high voltage v cc = min, i oh = ?1.0 ma 2.3 ? v v ol output low voltage v cc = min, i ol = 1.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?3 +3 ? a i oz output leakage current gnd < v i < v cc , output disabled ?3 +3 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc ?80ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?15ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?10ma note 3. v il (min.) = ?2.0v and v ih (max) = v cc + 0.5 v for pulse durations of less than 20 ns.
cy7c1021cv26 document number: 38-05589 rev. *g page 6 of 17 capacitance parameter [4] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 2.6 v 8 pf c out output capacitance 8pf thermal resistance parameter [4] description test conditions 44-pin tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 76.92 ? c/w ? jc thermal resistance (junction to case) 15.86 ? c/w ac test loads and waveforms figure 3. ac test loads and waveforms [5] 2.6 v output r2 30 pf including jig and scope r1 1830 ? 1976 ? 2.6 v output 5 pf r 317 ?? r2 351 ?? high z characteristics: 90% 10% 2.6 v gnd 90% 10% all input pulses rise time: 1 v/ns fall time: 1 v/ns (c) (b) (a) notes 4. tested initially and after any design or proces s changes that may affect these parameters. 5. ac characteristics (except high z) are tested using the thevenin load shown in figure 3 (a). high z characteristics are tested fo r all speeds using the test load shown in figure 3 (c).
cy7c1021cv26 document number: 38-05589 rev. *g page 7 of 17 switching characteristics over the operating range parameter [6] description -15 unit min max read cycle t rc read cycle time 15 ? ns t aa address to data valid ? 15 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 15 ns t doe oe low to data valid ? 7 ns t lzoe oe low to low z [7] 0 ? ns t hzoe oe high to high z [7, 8] ? 7 ns t lzce ce low to low z [7] 3 ? ns t hzce ce high to high z [7, 8] ? 7 ns t pu [9] ce low to power-up 0 ? ns t pd [9] ce high to power-down ? 15 ns t dbe byte enable to data valid ? 7 ns t lzbe byte enable to low z 0 ? ns t hzbe byte disable to high z ? 7 ns write cycle [10] t wc write cycle time 15 ? ns t sce ce low to write end 10 ? ns t aw address set-up to write end 10 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 10 ? ns t sd data set-up to write end 8 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [11] 3 ? ns t hzwe we low to high z [11, 12] ? 7 ns t bw byte enable to end of write 9 ? ns notes 6. test conditions assume signal transition time of 2.6 ns or le ss, timing reference levels of 1.3 v, input pulse levels of 0 to 2.6 v. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (c) of figure 3 . transition is measured ? 500 mv from steady-state voltage. 9. this parameter is guaranteed by design and is not tested. 10. the internal write time of the memory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write, and the transition of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 12. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (c) of figure 3 on page 6 . transition is measured ? 500 mv from steady-state voltage.
cy7c1021cv26 document number: 38-05589 rev. *g page 8 of 17 switching waveforms figure 4. read cycle no. 1 [13, 14] figure 5. read cycle no. 2 (oe controlled) [14, 15] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb notes 13. device is continuously selected. oe , ce , bhe and/or ble = v il . 14. we is high for read cycle. 15. address valid prior to or coincident with ce transition low.
cy7c1021cv26 document number: 38-05589 rev. *g page 9 of 17 figure 6. write cycle no. 1 (ce controlled) [16, 17] figure 7. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce notes 16. data i/o is high-impedance if oe or bhe and/or ble = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high-impedance state.
cy7c1021cv26 document number: 38-05589 rev. *g page 10 of 17 figure 8. write cycle no. 3 (we controlled, low) switching waveforms (continued) oe t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
cy7c1021cv26 document number: 38-05589 rev. *g page 11 of 17 truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc )
cy7c1021cv26 document number: 38-05589 rev. *g page 12 of 17 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurations and features. the following table contai ns only the list of parts that are currently available. for a comple te listing of all options, visit the cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . speed (ns) ordering code package name package type operating range 15 cy7c1021cv26-15zsxe 51-85087 44-pin tsop type ii (pb-free) automotive cy7c1021cv26-15vxe 51-85082 44-pin (400-mil) molded soj (pb-free) cy7c1021cv26-15bae 51-8 5150 48-ball fbga (6 8 1 mm) (pb-free) cy7c1021cv26-15baet 51- 85150 48-ball fbga (6 8 1 mm) (pb-free) cy7c1021cv26-15vxet 51-85082 44-pin (400-mil) molded soj (pb-free) CY7C1021CV26-15ZSXET 51-85087 44-pin tsop type ii (pb-free) x = t or blank t = tape and reel; blank = tube temperature range: e = automotive pb-free package type: xx = zs or v or ba zs = 44-pin tsop type ii v = 44-pin (400-mil) molded soj ba = 48-ball fbga speed grade: 15 ns v26 = 2.6 v process technology ? 0.16 m part identifier technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c1021 c -15xx e v26 x cy 7 x
cy7c1021cv26 document number: 38-05589 rev. *g page 13 of 17 package diagrams figure 9. 44-pin tsop z4 4-ii package outline, 51-85087 figure 10. 44-pin soj (400 mils) v44.4 package outline, 51-85082 51-85087 *e 51-85082 *e
cy7c1021cv26 document number: 38-05589 rev. *g page 14 of 17 figure 11. 48-ball fbga (6 8 1 mm) bv48/bz48 package outline, 51-85150 package diagrams (continued) 51-85150 *h
cy7c1021cv26 document number: 38-05589 rev. *g page 15 of 17 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable fbga fine-pitch ball grid array i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small-outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter mw milliwatt ns nanosecond % percent pf picofarad vvolt wwatt
cy7c1021cv26 document number: 38-05589 rev. *g page 16 of 17 document history page document title: cy7c1021cv26, 1-mbit (64 k 16) static ram document number: 38-05589 rev. ecn no. issue date orig. of change description of change ** 238454 see ecn rkf new data sheet for automotive. *a 335861 see ecn syt added lead-free product information included the 44-lead (400-mil) molded soj v34 package *b 493543 see ecn nxr changed the description of i ix from input load current to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table updated ordering information table *c 2897087 03/22/10 aju removed obsolete pa rts from ordering information table updated package diagrams . *d 3057593 10/13/2010 pras updated ordering information and added ordering code definitions . updated package diagrams. *e 3098812 12/01/2010 pras added acronyms and units of measure . minor edits and updated in new template. *f 3277371 06/08/2011 aju updated pin configurations (included pin configurations for 44-pin soj and 48-ball fbga packages). *g 4141238 09/30/2013 vini updated package diagrams : spec 51-85087 ? changed revision from *c to *e. spec 51-85082 ? changed revision from *c to *e. spec 51-85150 ? changed revision from *f to *h. updated in new template. completing sunset review.
document number: 38-05589 rev. *g re vised september 30, 2013 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1021cv26 ? cypress semiconductor corporation, 2004-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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